powerconsumption in cmos

Power Dissipation Components in Digital CMOS Circuits

Power consumption in CMOS circuits can be divided into three main components: short-circuit power, switching power, and leakage power. Short-circuit power arises when a conducting path between supply and ground is formed. The pull-up and pull-down devices should to be sized properly to achieve approximately equal rise and fall time. This component of power consumption can be significant in precharge and evaluate circuits, e.g. dynamic circuits.

                        Switching power is a result of the power consumed in charging and discharging internal capacitances in the circuit. Leakage power is the power dissipated while the device is turned off. Leakage power has started to form a significant portion of the total power consumption as a result of the low threshold devices normally used in advanced DSM(deep sub-micron) technologies.

Figure shows the increase in static (leakage) power for different technology generations. It is apparent that static power is dramatically increasing with technology scaling.The ratio of leakage to total power is expected to exceed 50% in 45nm designs from about 10% in 90nm designs

Switching power

Switching power is the largest contributor to the total power dissipation in conventional CMOS technologies. It is a result of switching the junction, diffusion, and interconnect capacitances. Consider the CMOS inverter circuit in Figure . The parasitic capacitances are lumped into the output capacitor C. Consider the behavior of the circuit over one full clock cycle with the input going from VDD to zero and back to VDD. As the input switches from high to low, the NMOS pull-down transistor is turned OFF while the PMOS pull-up transistor is ON and capacitor C is charged. This charging process draws an energy equal to CVDD^2from the power supply. Half of this energy is dissipated immediately in the PMOStransistor, while the other half is stored on C. When the input switches from zero back to VDD, the NMOS pull-down turns ON and the capacitance C discharges through it. If the rise time of the input signal is slow, both PMOS and NMOS are simultaneously ON causing a short circuit current to flow. This slow rise/fall time should be avoided through proper transistors sizing.

Leakage power

leakage power is discussed in earlier postings leakage current in cmos

sources of leakage current

There are four main sources of leakage current in a CMOS transistor
1. Reverse-biased junction leakage current (Irev)
2. Gate induced drain leakage (Igidl)
3. Gate direct-tunneling leakage (Ig)
4. Subthreshold (weak inversion) leakage (Isub)

Reverse-biased junction leakage current

Parasitic diodes formed between the diffusion region of the transistor and substrate consumes power in the form of reverse bias current which is drawn from the power supply. Junction leakage results from minority carrier diffusion and drift near the edge of depletion regions, and also from generation of electron hole pairs in the depletion regions of reverse-bias junctions. When both n regions and p regions are heavily doped, as is the case for some advanced MOSFETs, there will also be junction leakage due to band-to-band tunneling (BTBT), i.e., electron tunneling from valence band of the p-side to the conduction band of the n-side.

In inverter when input is high NMOS transistor is ON and output voltage is discharged to zero. Now between drain and the n-well a reverse potential difference of Vdd is established which causes diode leakage through the drain junction. The n-well region of the PMOS transistor w.r.to p-type substrate is also reverse biased. This also leads to leakage current at the N-well junction.

BAND TO BAND TUNNELLING

The band-to-band tunneling (BTBT) leakage current, also called reverse-bias pn junction leakage currents, is the current flow between the source/drain (S/D) and the substrate through the parasitic reverse-biased pn-junction diode during the off- state MOSFET. If both S/D and substrate regions are heavily doped, band-to-band tunneling (BTBT) increases significantly since the electric field across the junction depletion region increases. If the high electric field (V>10^6 V/cm) is formed across the reverse-biased junctions of the source/drain (S/D) regions so that the voltage drop across the junction is bigger than the band gap of silicon, especially with increasing S/D voltage or reverse body bias, a significant amount of BTBT current flows through the S/D to substrate junctions. In nanometer devices, higher channel and S/D doping with shallow junction depths are required to minimize SCEs(short channel effects), which causes a significant increase in BTBT current

Gate induced drain leakage (Igidl)

The gate induced drain leakage (GIDL) is caused by high field effect in the drain junction of MOS transistors. For an NMOS transistor with grounded gate and drain potential at VDD, significant band bending in the drain allows electron-hole pair generation through avalanche multiplication and band-to-band tunneling. A deep depletion condition is created since the holes are rapidly swept out to the substrate. At the same time, electrons are collected by the drain, resulting in GIDL current. This leakage mechanism is made worse by high drain to body voltage and high drain to gate voltage

Gate direct-tunneling leakage

As transistor length and supply voltage are scaled down, gate oxide thickness must also be reduced to maintain effective gate control over the channel region. Unfortunately this results in an exponential increase in the gate leakage due to direct tunneling of electrons through the gate oxide. An effective approach to overcome the gate leakage currents while maintaining excellent gate control is to replace the currently-used silicon dioxide gate insulator with high-K dielectric material such as TiO2 and Ta2O5. Use of the high-k dielectric will allow a less aggressive gate dielectric thickness reduction while maintaining the required gate overdrive at low supply voltages.

Subthreshold Leakage

The subthreshold leakage is the drain-source current of a transistor operating in the weak inversion region. Unlike the strong inversion region in which the drift current dominates, the subthreshold conduction is due to the diffusion current of the minority carriers in the channel for a MOS device.For instance, in the case of an inverter with a low input voltage, the NMOS is turned OFF and the output voltage is high. In this case, although VGS is 0V, there is still a current flowing in the channel of the OFF NMOS transistor due to the VDD potential of the VDS. The magnitude of the subthreshold current is a function of the temperature, supply voltage, device size, and the process parameters out of which the threshold voltage (VT) plays a dominant role