low power techniques

The  various low power techniques into 2 categories

(a)Structural Techniques
Voltage Islands
Multi-threshold devices
Multi-oxide devices
Minimize capacitance by custom design
Power efficient circuits
Parallelism in micro-architecture
(b)Traditional Techniques
Clock gating
Power gating
Variable frequency
Variable voltage supply
Variable device threshold
Dynamic Power Reduction
Clock Gating
Power efficient circuits
Variable frequency
Variable voltage supply
Leakage Power Reduction
Minimize usage of Low Vt Cells
Power Gating
Back Biasing
Reducing Dynamic Power
Reduce Oxide Thickness
Use FINFET’s
The techniques will discussed in detail future posts

powerconsumption in cmos

Power Dissipation Components in Digital CMOS Circuits

Power consumption in CMOS circuits can be divided into three main components: short-circuit power, switching power, and leakage power. Short-circuit power arises when a conducting path between supply and ground is formed. The pull-up and pull-down devices should to be sized properly to achieve approximately equal rise and fall time. This component of power consumption can be significant in precharge and evaluate circuits, e.g. dynamic circuits.

                        Switching power is a result of the power consumed in charging and discharging internal capacitances in the circuit. Leakage power is the power dissipated while the device is turned off. Leakage power has started to form a significant portion of the total power consumption as a result of the low threshold devices normally used in advanced DSM(deep sub-micron) technologies.

Figure shows the increase in static (leakage) power for different technology generations. It is apparent that static power is dramatically increasing with technology scaling.The ratio of leakage to total power is expected to exceed 50% in 45nm designs from about 10% in 90nm designs

Switching power

Switching power is the largest contributor to the total power dissipation in conventional CMOS technologies. It is a result of switching the junction, diffusion, and interconnect capacitances. Consider the CMOS inverter circuit in Figure . The parasitic capacitances are lumped into the output capacitor C. Consider the behavior of the circuit over one full clock cycle with the input going from VDD to zero and back to VDD. As the input switches from high to low, the NMOS pull-down transistor is turned OFF while the PMOS pull-up transistor is ON and capacitor C is charged. This charging process draws an energy equal to CVDD^2from the power supply. Half of this energy is dissipated immediately in the PMOStransistor, while the other half is stored on C. When the input switches from zero back to VDD, the NMOS pull-down turns ON and the capacitance C discharges through it. If the rise time of the input signal is slow, both PMOS and NMOS are simultaneously ON causing a short circuit current to flow. This slow rise/fall time should be avoided through proper transistors sizing.

Leakage power

leakage power is discussed in earlier postings leakage current in cmos