sources of leakage current

There are four main sources of leakage current in a CMOS transistor
1. Reverse-biased junction leakage current (Irev)
2. Gate induced drain leakage (Igidl)
3. Gate direct-tunneling leakage (Ig)
4. Subthreshold (weak inversion) leakage (Isub)

Reverse-biased junction leakage current

Parasitic diodes formed between the diffusion region of the transistor and substrate consumes power in the form of reverse bias current which is drawn from the power supply. Junction leakage results from minority carrier diffusion and drift near the edge of depletion regions, and also from generation of electron hole pairs in the depletion regions of reverse-bias junctions. When both n regions and p regions are heavily doped, as is the case for some advanced MOSFETs, there will also be junction leakage due to band-to-band tunneling (BTBT), i.e., electron tunneling from valence band of the p-side to the conduction band of the n-side.

In inverter when input is high NMOS transistor is ON and output voltage is discharged to zero. Now between drain and the n-well a reverse potential difference of Vdd is established which causes diode leakage through the drain junction. The n-well region of the PMOS transistor w.r.to p-type substrate is also reverse biased. This also leads to leakage current at the N-well junction.

BAND TO BAND TUNNELLING

The band-to-band tunneling (BTBT) leakage current, also called reverse-bias pn junction leakage currents, is the current flow between the source/drain (S/D) and the substrate through the parasitic reverse-biased pn-junction diode during the off- state MOSFET. If both S/D and substrate regions are heavily doped, band-to-band tunneling (BTBT) increases significantly since the electric field across the junction depletion region increases. If the high electric field (V>10^6 V/cm) is formed across the reverse-biased junctions of the source/drain (S/D) regions so that the voltage drop across the junction is bigger than the band gap of silicon, especially with increasing S/D voltage or reverse body bias, a significant amount of BTBT current flows through the S/D to substrate junctions. In nanometer devices, higher channel and S/D doping with shallow junction depths are required to minimize SCEs(short channel effects), which causes a significant increase in BTBT current

Gate induced drain leakage (Igidl)

The gate induced drain leakage (GIDL) is caused by high field effect in the drain junction of MOS transistors. For an NMOS transistor with grounded gate and drain potential at VDD, significant band bending in the drain allows electron-hole pair generation through avalanche multiplication and band-to-band tunneling. A deep depletion condition is created since the holes are rapidly swept out to the substrate. At the same time, electrons are collected by the drain, resulting in GIDL current. This leakage mechanism is made worse by high drain to body voltage and high drain to gate voltage

Gate direct-tunneling leakage

As transistor length and supply voltage are scaled down, gate oxide thickness must also be reduced to maintain effective gate control over the channel region. Unfortunately this results in an exponential increase in the gate leakage due to direct tunneling of electrons through the gate oxide. An effective approach to overcome the gate leakage currents while maintaining excellent gate control is to replace the currently-used silicon dioxide gate insulator with high-K dielectric material such as TiO2 and Ta2O5. Use of the high-k dielectric will allow a less aggressive gate dielectric thickness reduction while maintaining the required gate overdrive at low supply voltages.

Subthreshold Leakage

The subthreshold leakage is the drain-source current of a transistor operating in the weak inversion region. Unlike the strong inversion region in which the drift current dominates, the subthreshold conduction is due to the diffusion current of the minority carriers in the channel for a MOS device.For instance, in the case of an inverter with a low input voltage, the NMOS is turned OFF and the output voltage is high. In this case, although VGS is 0V, there is still a current flowing in the channel of the OFF NMOS transistor due to the VDD potential of the VDS. The magnitude of the subthreshold current is a function of the temperature, supply voltage, device size, and the process parameters out of which the threshold voltage (VT) plays a dominant role

short channel effects in mosfets

As the channel length L is reduced to increase both the operation speed and the number of

components per chip, the so-called short-channel effects arise.

Short-Channel Effects

The short-channel effects are attributed to two physical phenomena:

1. the limitation imposed on electron drift characteristics in the channel,

2. the modification of the threshold voltage due to the shortening channel length.

In particular five different short-channel effects can be distinguished:

1. drain-induced barrier lowering and punchthrough

2. surface scattering

3. velocity saturation

4. impact ionization

5. hot electrons

Drain-induced barrier lowering and punchthrough

In a MOSFET device with improperly scaled small channel length and too low channel doping, undesired electrostatic interaction can take place between the source and the drain known as drain-induced barrier lowering (DIBL) takes place. This leads to punch-through leakage or breakdown between the source and the drain, and loss of gate control. One should consider the surface potential along the channel to understand the punch-through phenomenon. As the drain bias increases, the conduction band edge (which represents the electron energies) in the drain is pulled down, leading to an increase in the drain-channel depletion width

In a long-channel device, the drain bias does not influence the source-to-channel potential barrier, and it depends on the increase of gate bias to cause the drain current to flow. However, in a short-channel device, as a result of increase in drain bias and pull-down of the conduction band edge, the source-channel potential barrier is lowered due to DIBL. This in turn causes drain current to flow regardless of the gate voltage (that is, even if it is below the threshold voltage V_th). More simply, the advent of DIBL may be explained by the expansion of drain depletion region and its eventual merging with source depletion region, causing punch-through breakdown between the source and the drain. The punch-through condition puts a natural constraint on the voltages across the internal circuit nodes.

Sub-threshold region conduction : the cutoff region of operation is also referred to as the sub-threshold region, which is mathematically expressed as I_DS =0 V_GS <>_{th. However, a phenomenon called sub-threshold conduction is observed in small-geometry transistors. The current flow in the channel depends on creating and maintaining an inversion layer on the surface. If the gate voltage is inadequate to invert the surface (that is, VGS< VT0 ), the electrons in the channel encounter a potential barrier that blocks the flow. However, in small-geometry MOSFETs, this potential barrier is controlled by both VGS and VDS . If the drain voltage is increased, the potential barrier in the channel decreases, leading to drain-induced barrier lowering (DIBL). The lowered potential barrier finally leads to flow of electrons between the source and the drain, even if VGS < VT0 (that is, even when the surface is not in strong inversion). The channel current flowing in this condition is called the sub-threshold current . This current, due mainly to diffusion between the source and the drain, is causing concern in deep sub-micron designs.}

Surface scattering

As the channel length becomes smaller due to the lateral extension of the depletion layer into the

channel region, the longitudinal electric field component ey increases, and the surface mobility

becomes field-dependent. Since the carrier transport in a MOSFET is confined within the narrow inversion layer, and the surface scattering (that is the collisions suffered by the electrons that are accelerated toward the interface by ex) causes reduction of the mobility, the electrons move with great difficulty parallel to the interface, so that the average surface mobility, even for small values of ey, is about half as much as that of the bulk mobility

Velocity saturation

As devices are reduced in size, the electric field typically also increases and the carriers in the channel have an increased velocity. However at high fields there is no longer a linear relation between the electric field and the velocity as the velocity gradually saturates reaching the saturation velocity.This velocity saturation is caused by the increased scattering rate of highly energetic electrons.

Hot electrons

The resulting increase in the electrical field strength causes an increasing velocity of the electrons, which can leave the silicon and tunnel into the gate oxide upon reaching a high-enough energy level. Electrons trapped in the oxide change the threshold voltage, typically increasing the thresholds of NMOS devices, while decreasing the VT of PMOS transistors. For an electron to become hot, an electrical field of at least 10⁴ V/cm is necessary. This condition is easily met in devices with channel lengths around or below 1u mm. The hot-electron phenomenon can lead to a long-term reliability problem, where a circuit might degrade or fail after being in use for a while.

As the gate-oxide is scaled down, breakdown of the oxide and oxide reliability becomes more of a concern. Higher fields in the oxide increase the tunneling of carriers from the channel into the oxide. These carriers slowly degrade the quality of the oxide and lead over time to failure of the oxide. This effect is referred to as time dependent destructive breakdown (TDDB) Impact ionization Another undesirable short-channel effect, especially in NMOS, occurs due to the high velocity of electrons in presence of high longitudinal fields that can generate electron-hole (e-h) pairs by impact ionization, that is, by impacting on silicon atoms and ionizing them.It happens as follow: normally, most of the electrons are attracted by the drain, while the holes enter the substrate to form part of the parasitic substrate current. Moreover, the region between the source and the drain can act like the base of an npn transistor, with the source playing the role of the emitter and the drain that of the collector. If the aforementioned holes are collected by the source, and the corresponding hole current creates a voltage drop in the substrate material of the order of .6V, the normally reversed-biased substrate-source pn junction will conduct appreciably. Then electrons can be injected from the source to the substrate, similar to the injection of electrons from the emitter to the base. They can gain enough energy as they travel toward the drain to create new e-h pairs. The situation can worsen if some electrons generated due to high fields escape the drain field to travel into the substrate, thereby affecting other devices on a chip.